The present invention relates to a data processor for detecting an error that has been produced in data being transferred.
Recently, microcontrollers for use in various types of controls have their size or operating voltage reduced considerably, and have their immunity against extraneous noise decreased correspondingly. So as is more and more often the case with microcontrollers of today, extraneously incoming noise partially alters data transferred, thereby causing a system runaway. Under the circumstances such as these, first of all, microcontrollers should have their noise immunity improved. But it is no less important to minimize the damage potentially done on the system by the noise-induced runaway so that the system can resume running normally as quickly as possible.
Hereinafter, it will be described with reference to FIG. 12 how a known data processor operates. FIG. 12 is a block diagram illustrating an arrangement for a known data processor.
As shown in FIG. 12, the processor includes microcontroller 130, memories 110 and 120 and data buses 31, 32 and 33. The memories 110 and 120 and microcontroller 130 are connected to the data buses 31, 32 and 33, respectively. The data buses 31 and 32 are coupled together via a bus switch 34, while the data buses 32 and 33 are coupled together via a bus switch 35.
Suppose the microcontroller 130 is now reading a program from the memory 110 and, executing it, and the program stored on the memory 110 is represented by data xe2x80x9c55hxe2x80x9d, where h indicates that this is a hexadecimal representation. In that case, the data is transferred from the memory 110 to the microcontroller 130 by way of the buses 31, 32 and 33. On receiving the data, the microcontroller 130 decodes it to execute the program.
For example, assume the data xe2x80x9c55hxe2x80x9d is affected by extraneous noise and changes into xe2x80x9c54hxe2x80x9d while transferred through the bus 32. Even so, the microcontroller 130 also decodes the erroneous data xe2x80x9c54hxe2x80x9d as usual to execute the program just as decoded. In that case, the microcontroller 130 will not operate as originally intended by the program.
In a data processor like this, even if data is affected by noise and subjected to unwanted change while being transferred, the device on the receiving end will continue to operate erroneously, because the receiver has no means for detecting the unintentional data change. For example, where a microcontroller should receive data representing a program, the unwanted data change will force the microcontroller to execute the erroneous program continuously against the original purpose. As a result, the data processor adversely causes a runaway or is hung up unintentionally.
An object of this invention is providing a data processor that detects any change caused by extraneous noise in data being transferred through a signal path, like a data bus, and thereby resumes running normally even if the processor once operated erroneously due to the data change.
Specifically, a first inventive data processor includes first and second devices that are coupled together via a signal path. The first device includes a first arithmetic unit. The first arithmetic unit performs an arithmetic operation on data to obtain a first result during an operation cycle in which the first device transfers the data to the second device through the signal path. The first arithmetic unit outputs the first result onto the signal path during an idle cycle in which no data is transferred through the signal path. The second device includes a second arithmetic unit and a comparator. The second arithmetic unit performs the same type of arithmetic operation on the data, transferred through the signal path in the operation cycle, to obtain a second result. And the comparator compares the first result, transferred through the signal path in the idle cycle, to the second result and outputs a comparison result.
The first inventive processor performs an arithmetic operation based on the value of data on a signal path in an operation cycle, and transfers a result of the operation to the second device and compares the result to another operation result in an idle cycle. Accordingly, a data change caused by extraneous noise can be detected without taking any time for error detection.
In one embodiment of the present invention, if the comparison result indicates inequality between the first and second results, the comparator may initialize the second device by performing interrupt or reset processing. In such an embodiment, if the first and second results compared do not agree with each other, then the second device is initialized by supplying an interrupt or reset signal thereto. Accordingly, even if the second device has caused a runaway due to extraneous noise, the second device can soon resume running normally. Where the second device is a microcontroller, for example, an erroneous program can be aborted and an intended program can be executed correctly.
In another embodiment of the present invention, the inventive processor may further include a controller. The controller may count the number of times of inequality between the first and second results. The controller may output an interrupt signal to the second device if the number is equal to or smaller than a predetermined number or a reset signal to the second device if the number is greater than the predetermined number. In such an embodiment, if the comparison results indicate inequality a relatively small number of times, then the second device can be initialized by means of software, or by executing interrupt-driven processing. On the other hand, if the comparison results indicate inequality a relatively large number of times, then the hardware, or the second device, can be reset and initialized compulsorily. In this manner, the second device can be adaptively rebooted in accordance with the situation.
In still another embodiment, the inventive processor may further include a frequency divider. The frequency divider may supply a signal, a frequency of which is a submultiple of a clock frequency, to the second device and decrease the frequency of the signal if the comparison result indicates inequality between the first and second results. In such an embodiment, the level of the noise generated inside the second device can be lowered gradually by decreasing the operating speed of the second device.
In yet another embodiment, the first device may be a memory device and the second device may be a microcontroller. In such an embodiment, any change caused by extraneous noise in data being transferred from the memory device to the microcontroller can be detected.
A second inventive data processor includes first and second devices that are coupled together via a signal path. The first device includes a first arithmetic unit and a comparator. The first arithmetic unit performs an arithmetic operation on data to obtain a first result during an operation cycle in which the first device transfers the data to the second device through the signal path. The second device includes a second arithmetic unit. The second arithmetic unit performs the same type of arithmetic operation on the data, transferred through the signal path in the operation cycle, to obtain a second result and outputs the second result onto the signal path during an idle cycle in which no data is transferred through the signal path. And the comparator compares the second result, transferred through the signal path in the idle cycle, to the first result and outputs a comparison result.
The second inventive processor performs an arithmetic operation based on the value of data on a signal path in an operation cycle, and transfers a result of the operation to the first device and compares the result to another operation result in an idle cycle. Accordingly, a data change caused by extraneous noise can be detected without taking any time for error detection.
A third inventive data processor includes: first, second and third devices that are coupled together via a signal path having a number of sections; and the same number of drivers for driving the respective sections of the signal path. The third device is connected to one of the sections that are located between the sections to which the first and second devices are respectively connected. The first device includes a first arithmetic unit. The first arithmetic unit performs an arithmetic operation on data to obtain a first result during an operation cycle in which the first device transfers the data to the second device through the signal path. The first arithmetic unit outputs the first result onto the signal path during an idle cycle in which no data is transferred through the signal path. The second device includes a second arithmetic unit and a sequencer. The second arithmetic unit performs the same type of arithmetic operation on the data, transferred through the signal path in the operation cycle, to obtain a second result. The third device includes a third arithmetic unit. The third arithmetic unit also performs the same type of arithmetic operation on the data, transferred through the signal path in the operation cycle, obtains a third result and then outputs the third result to the sequencer. The sequencer compares the first, second and third results to each other in the idle cycle. Also, the sequencer selectively increases the drivability of one of the drivers that drives either the section connected to the third device if the first result, transferred through the signal path, is different from the third result or the section connected to the second device if the second and third results are different from each other.
The third inventive processor can locate a specific signal path section in which data being transferred is affected by extraneous noise, and selectively increases the drivability of the driver associated with the section in question. In this manner, the processor can have its noise immunity improved without increasing the power dissipation too much.
In one embodiment of the present invention, the first and third devices may be memory devices and the second device may be a microcontroller. In such an embodiment, the processor exhibits improved noise immunity in transferring data from one of the memory devices to the microcontroller.